A Scalable Implementation of Virtual Memory HAT Layer for Shared Memory Multiprocessor Machines

This paper describes the design and implementation of the UNIX@ SVR4.2 Virtual Memory (VM) Hardware Address Translation (ÌIAT) layer that can be used as a model for other multiprocessor (MP) platforms in terms of scalability and MP related interfaces between the IIAT layer and the machine independent layer. SVR4.2 is a SVR4.1 ES based kernel that suppo¡s shared memory multiprocessors and light weight processes in a shared address space. By implementing a fine-grained locking mechañisn¡ a lazy Translation Lookaside Buffer (TLB) shootdown evaluation policy and other improvements over the SVR4 design _ the memory management feature is made scalable in terml of number of processors as well as size of memory supported. Providing a small set of interfaces beiween the machine dependent and independent layers for TLB consistency and a simple set of locking requirements between th€ two layers, SVR4.2 facilitates thè portability of the memory management feature to other multiprocessor platforms.